This application is based upon and claims the benefit of priority from the prior Japanese Patent application No. 2000-329264, filed Oct. 27, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a dynamic random access memory (hereinafter referred to as a DRAM) capable of retaining data with low power consumption.
To retain data for a long time, the DRAM has to execute a refresh operation. This operation is necessary for the DRAM, due to the inherent characteristic of the memory cells of the DRAM. In general, the refresh operation of a DRAM includes two kinds of operations: one is a refresh operation executed in response to a trigger signal supplied from outside a chip (i.e., an auto refresh operation); and the other is a refresh operation executed in response to a trigger signal generated inside the chip (i.e., a. self refresh operation).
Let us consider the case of a 64-Mbit synchronous DRAM by way of example. In this type of DRAM, a trigger signal (an auto refresh command) has to be supplied into a chip 4,096 times during a period of 64 ms, and a refresh operation has to be executed for all memory cells of the 64-Mbit DRAM during that period.
In other words, the longest refresh interval, i.e., the interval between the time when one memory cell is refreshed and the time when the same memory cell is refreshed again, is 64 ms.
Hence, the characteristic of reliably retaining data at least during this 64 ms period (i.e., a so-called xe2x80x9cpause time characteristicxe2x80x9d) is essential to each memory cell.
Normally, a refresh operation is executed in units of one row, and the one-time refresh operation enables the data in the memory cells of one row to be refreshed by means of a sense amplifier. If the memory capacity of a memory cell ray is n bits (a: being a constant), the number of memory cells refreshed in the one-time refresh operation is in bits (in: being a constant), and the refresh interval is tR seconds, ten the number N of times the refresh operation is executed per unit time is expressed by:
N=n/(mxc2x7tR)xe2x80x83xe2x80x83(1) 
Let us assume that each memory cell consumes the same amount of current for the refresh operation and that the current consumption m is constant throughout the refresh operation (m: a constant). In this case, the total amount of current consumed in the refresh operation can be reduced by lengthening the refresh interval tR and reducing the number of times the refresh operation is executed per unit time.
For example, in the cell refresh operation, an arbitrary refresh interval tR can be freely selected within a chip. It should be also noted that when a DRAM having a self-refresh function is being used, the amount of current consumed for the self-refresh operation must be as small as possible. In this type of DRAM, therefore, the refresh interval tR is controlled to be the longest value within the range which the characteristics (the pause time characteristic) of the memory cells allow.
More specifically, if the pause time characteristic of the memory cells is 64 ms, the refresh interval tR at the time of the self refresh operation is set at 64 ms, which is a maximal value within the setting range. Likewise, if the pause time characteristic of the memory cells is 128 ms, the refresh interval tR at the time of the self refresh operation is set at 128 ms.
Where the pause time characteristic of the memory cells is 128 ms, the number N of times the refresh operation is executed per unit time can be reduced by one half in comparison with the case where the pause time characteristic is 64 ms. As a result, the amount of current consumed for the refresh operation can be reduced by one half.
The number N of times the refresh operation is executed per unit time can be given by formula (1) set forth above. As one way to reduce the total amount of current consumed in the refresh operation, it is thought to lengthen the refresh interval tR to a maximal value within the range the pause time characteristic allows, and to reduce the number N of times the refresh operation is executed per unit time.
However, the refresh interval tR depends on the pause time characteristics of memory cells. It follows from this that the pause time characteristic of the memory cells has to be improved in order to ensure a long refresh interval tR. In terms of the device structure, however, it is very difficult to improve the pause time characteristic of the memory cells to such an extent as to significantly reduce the amount of current consumed for the refresh operation.
A semiconductor memory according to an aspect of the present invention comprises: a memory cell array; a signal generation circuit which generates an internal address signal used for selecting rows of the memory cell array at the time of a refresh operation; and a control circuit which fixes the value of at least one of the bits of the internal address signal on the basis of a first control signal and selects the rows in a refresh area whose memory capacity is smaller than that of the memory cell array, at the time of the refresh operation.
Another semiconductor memory according to an aspect of the present invention comprises: a memory cell array; a signal generation circuit which generates an internal address signal used for selecting rows of the memory cell array at the time of a refresh operation; a control circuit which selects rows in a refresh area whose memory capacity is smaller than that of the memory cell array on the basis of a first control signal at the time of the refresh operation; and a refresh timer which determines refresh execution timings, wherein, when the rows in the refresh area are selected, the refresh timer switches the refresh execution timings and changes timings for selecting the rows in the refresh area.